This invention relates generally to the stress testing of integrated circuits (IC's) by applying higher-than-normal voltages and/or temperatures to them over a period of several days in specially designed burn-in trays [which are actually specially designed printed circuit boards (PCBs)] which are placed in an oven and subjected to higher-than-normal voltages and/or temperatures, and more particularly to an improved multilayered PCB tray design which permits the testing of almost twice as many IC's in a given sized oven as was possible with prior art trays.
In the prior art devices the IC's are inserted in individual sockets which in turn have pin terminals which plug into the burn-in tray. The prior art devices employ a plurality of discrete current limiting resistors which isolate the various IC terminals from an exciting signal or stress voltage. The number of discrete resistors required for each IC will vary with different IC's but a typical number might be of the order of 12-16 such resistors for each IC.
Since there are usually a large number of IC's mounted on each PCB tray, for example from 100 to 250 IC's per tray, it can be seen that the number of discrete resistors can be quite large, of the order of 1200 to 4000, each of which must be hand-wired in place between a terminal in the tray, and a socket terminal which is connected to an IC terminal. The cost of such a large number of resistors per tray, and there can be many such trays being tested simultaneously, plus the labor cost of hand wiring each resistor in place amounts to a sizable increase in the cost of stress testing the IC's. In addition the cost of each oven is of the order of $60,000 to $80,000 which is substantial even when it is considered that each oven has a life expectancy of several years.
An example of the prior art method of stress testing IC's is shown in one of the figures of the present specification.
It can be seen that the use of discrete isolating resistors is not only costly from a viewpoint of materials and labor but also limits the number of IC's that can be stress tested on a single tray because of the space required for the discrete resistors.
The prior art shown in one of the figures herein is made by EG and G Wakefield Systems of Wakefield, Massachusetts. Further information regarding this prior art technique can be obtained from the Wakefield Systems Company, including information concerning the type IC's that are stress tested by the prior art technique described generally above but also the number of each different type of IC that various type trays will hold.